Fpga lookup table with high speed read decoder

Details Fpga lookup table with high speed read decoder Fpga lookup table with high speed read decoder

H - Electricity

03

K

H03K 19/177 (2006.01) H03K 19/173 (2006.01)

Patent

CA 2411650

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and second LUT.

L'invention concerne une table de recherche rapide occupant l'espace efficacement et convenant pour des unit~s logiques programmables dans lesquelles le d~codeur d'~criture, le d~codeur de lecture et le bloc m~moire de la table de recherche sont modifi~s afin d'am~liorer le rendement de cette derni­re, tout en permettant une disposition hautement performante. Tant le d~codeur d'~criture que le d~codeur de lecture sont command~s par des signaux d'entr~e de la table de recherche et des signaux de donn~es sont directement transmis ~ chaque circuit de m~moire du bloc m~moire (c'est-~-dire, sans passer par le d~codeur d'~criture). Le d~codeur de lecture comprend un circuit de multiplexage constitu~ d'une s~rie de multiplexeurs directement command~s par les signaux d'entr~e re×us des ressources d'interconnexion de l'unit~ logique programmable. Dans un mode de r~alisation, un bloc logique configurable est pourvu d'un seul d~codeur d'~criture partag~ par une premi­re table de recherche et par une seconde table de recherche.

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