Frame aligner with reduced circuit scale

Details Frame aligner with reduced circuit scale Frame aligner with reduced circuit scale

H - Electricity

04

L

H04L 7/10 (2006.01) H04J 3/06 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2100179

ABSTRACT OF THE DISCLOSURE A frame aligner detects sync patterns consisting of at least two units of data having a first value followed by at least two units of data having a second value in a serial data signal. The serial signal is demultiplexed to units of parallel data, which are stored in a shift register having a capacity of two units of data. All but one bit of the stored data are scanned to detect a unit having the first value. When such a unit is detected, alignment data indicating its position in the shift register are generated, The alignment data are latched and used to extract subsequent units from the shift register. New and old alignment data are compared to detect aligned units having the first value. A sync pattern is recognized as a consecutive sequence of such aligned units followed by a consecutive sequence of units having the second value.

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