Frame bit-size allocation for seamlessly spliced,...

Details Frame bit-size allocation for seamlessly spliced,... Frame bit-size allocation for seamlessly spliced,...

H - Electricity

04

N

H04N 7/26 (2006.01) H04N 7/50 (2006.01) H04N 7/24 (2006.01)

Patent

CA 2365365

A controller allocates a bit size for a current frame in a group of pictures of a first compression-encoded digital video signal that is to be spliced following transmission of the group of pictures with a second compression-encoded digital video signal. The signals are spliced after a predetermined switching time. The spliced signals are buffered by a decoder buffer and then decoded by a decoder. When the second signal has a variable bit-encoding rate and the current frame is not decoded until after the predetermined switching time, the maximum bit size is determined in accordance with an estimate of the decoder buyer fullness at the predetermined switching time. When the second signal has a predetermined maximum variable bit-encoding rate and the current frame is not decoded until after the predetermined switching time, the minimum bit size is determined in accordance with the predetermined maximum bit-encoding rate of the second signal.

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