Frame buffer memory

Details Frame buffer memory Frame buffer memory

G - Physics

09

G

354/241

G09G 1/16 (2006.01) G09G 5/34 (2006.01) G09G 5/393 (2006.01)

Patent

CA 1258716

37 Abstract A frame buffer memory has a random access memory (RAM) for storing pixel data words, each word con- taining pixel data corresponding to a separate set of a plurality pixels along a horizontal raster line of a screen display. Each word is separately addressed. The RAM is organized into tiles, with each tile comprising an array of pixel data word rows and columns corresponding to a separate rectangular sub- set of horizontally and vertically contiguous display pixels. The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel word row within each tile is addressed, while and a second subset of the column address determines which pixel word column within each tile is addressed. All other bits of the row and column addresses deter- mine which tile is addressed. Means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that words within a selected tile row or column may be successively addressed allowing rapid reading and writing of sequences of pixel data corresponding to contiguous rows or columns of dis- play pixels. A first-in, first-out buffer, provided to store the sequences of data read from the RAM, also includes a barrel shifter to shift bit positions of the data words so stored to facilitate proper pixel alignment during a horizontal scrolling operation. A logic circuit is provided to rapidly modify sequences of data read from the RAM and stored in the buffer prior to rewriting the data to the RAM thereby allowing rapid alteration of pixel attributes.

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