Frame buffer memory controller

Details Frame buffer memory controller Frame buffer memory controller

G - Physics

09

G

354/237

G09G 1/16 (2006.01) G09G 5/39 (2006.01)

Patent

CA 1264496

-13- Abstract of the Disclosure A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

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