Frame resynchronization circuit for digital receiver

Details Frame resynchronization circuit for digital receiver Frame resynchronization circuit for digital receiver

H - Electricity

04

J

363/17

H04J 3/06 (2006.01) H04L 7/04 (2006.01)

Patent

CA 1167185

- 26 - FRAME RESYNCHRONIZATION CIRCUIT FOR DIGITAL RECEIVER Abstract Framing of a digital receiver to synchronize with a true framing pattern is realized by employing an autonomous clock to generate framing pattern bits and other timing signal, and by employing a cyclical-redundancy-check (CRC) to eliminate the possibility of framing on false framing patterns. To this end, a frame synchronization circuit detects all possible framing candidate bit positions in a received time division signal and generates a frame resynchronization pulse corresponding to the framing candidate bit positions thereby causing the autonomous clock to synchronize to the associated framing pattern. If the framing pattern on which the clock is synchronized is a false one a loss of CRC signal is generated which initiates synchronizing on the next detected framing pattern. This process is iterated until no loss of CRC signal is generated thereby indicating synchronization on the true framing pattern.

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