Frame synchronization with slip compensation

Details Frame synchronization with slip compensation Frame synchronization with slip compensation

H - Electricity

04

J

363/17

H04J 3/06 (2006.01) H04L 7/00 (2006.01) H04L 7/08 (2006.01)

Patent

CA 1262384

FRAME SYNCHRONIZATION WITH SLIP COMPENSATION Abstract of the Disclosure Frame synchronization to the framing pattern of a DS3 bit stream is achieved by detecting the framing pattern and producing a synchronizing slip in the absence of such detection. In order to avoid long framing times as a result of unconfigured adjacent DS1 transmission links producing data which mimic the DS3 framing pattern, redundantly transmitted stuff information (tributary justification control) bits are also checked to ensure that appropriate bits, relative to the position of the framing pattern bits, have expected properties (e.g. triplicated values), and a synchronizing slip is also produced if this is not the case. Short framing times are also achieved by storing in each of the framing pattern and stuff information bit detectors not only the particular bits which are currently to be checked, but also consecutive bits which are selected in dependence upon the occurrence of previous synchronizing slips. -i-

475839

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