Framing algorithm for bit interleaved time division multiplexer

H - Electricity – 04 – J

Patent

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363/10

H04J 3/16 (2006.01)

Patent

CA 1320289

ABSTRACT OF THE DISCLOSURE Methods are provided for multiplexing a plurality of channels onto a sub-aggregate of and aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACS compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S)F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame. Where different primary frame rates may be used, the sum of (A/P) plus (P/S)F1 plus (S/T)F2 is minimized to find primary and secondary frame rates which will permit an optimally small total frame length, given the sub-aggregate rate A.

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