Framing circuit for digital receiver

Details Framing circuit for digital receiver Framing circuit for digital receiver

H - Electricity

04

J

363/17

H04J 3/06 (2006.01)

Patent

CA 1166775

- 24 - FRAMING CIRCUIT FOR DIGITAL RECEIVER Abstract The possibility of framing a receiver on a false pattern either generated, for example, by a data subscriber, or simply one statistically occurring in the normal digital transmission is minimized by employing a cyclical-redundancy-check (CRC). Bits of a presently received time division signal are compared to bits of a CRC code word generated from the last previously received block of bits of the time division signal to generate error indications. When a predetermined number of CRC error indications is detected, i.e., loss of CRC, the framing bit pattern the receiver is synchronized with is considered a false pattern and reframing of the receiver is initiated. This process is iterated until no loss of CRC is detected for the framing bit pattern that the receiver is synchronized with. In a specific example, a 6-bit CRC code word is employed.

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