Frequency doubler with 50 percent duty cycle output

H - Electricity – 03 – K

Patent

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328/17

H03K 5/00 (2006.01) H03K 5/156 (2006.01)

Patent

CA 1217826

FREQUENCY DOUBLER WITH FIFTY PERCENT DUTY CYCLE OUTPUT SIGNAL Yusuf A. Haque ABSTRACT A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substan- tial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.

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