Frequency doubler with a variable delay circuit and...

Details Frequency doubler with a variable delay circuit and... Frequency doubler with a variable delay circuit and...

H - Electricity

03

K

H03K 19/21 (2006.01) H03K 3/017 (2006.01) H03K 5/00 (2006.01)

Patent

CA 2067562

A doubling circuit for adjusting the duty ratio of an output signal automatically and implemented as a digital circuit. A variable delay circuit delays an input signal while an exclusive-OR (EOR) gate produces EOR of the output signal of the delay circuit and the input signal. The resulting output of the EOR gate has a frequency double the frequency of the input signal. A low pass filter (LPF) filters the output signal of the EOR gate to produce a mean voltage thereof. An integrating circuit integrates a difference between the output voltage of the LPF and a reference voltage. The delay of the variable delay circuit is controlled by the output of the integrating circuit. As a result, the doubled signal from the EOR gate has the duty ratio thereof automatically adjusted.

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