Frequency-doubling delay locked loop

Details Frequency-doubling delay locked loop Frequency-doubling delay locked loop

H - Electricity

03

K

H03K 5/14 (2006.01) H03K 3/027 (2006.01) H03K 5/15 (2006.01)

Patent

CA 2270516

This invention relates to a delay locked loop that generates an output clock signal in response to a reference input clock signal comprises several components. A delay line having a plurality of serially coupled delay stages, provides a delay stage tap output from each of the delay stages. Each of the delay stage tap outputs is coupled to a one of a plurality of combining circuit cells. The combining cells each have the same predetermined number of inputs and provide a pair of complementary outputs. The outputs of each cell are separated in time in relation to the number of cell inputs. A selector responsive to a selection control signal selects an output from one of a pair of complementary outputs from one of the combining cells, to produce said output clock signal. A phase detector responsive to the output signal and the reference input clock signal to control the selector for selecting an optimum output for synchronizing the reference input clock signal and the said output clock signal.

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