Full address and odd boundary direct memory access controller

Details Full address and odd boundary direct memory access controller Full address and odd boundary direct memory access controller

G - Physics

06

F

354/236, 354/239

G06F 12/02 (2006.01) G06F 13/28 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2007443

FULL ADDRESS AND ODD BOUNDARY DIRECT MEMORY ACCESS CONTROLLER Abstract of the Disclosure The computer system disclosed includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DNA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

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