Fully scalable memory apparatus

Details Fully scalable memory apparatus Fully scalable memory apparatus

G - Physics

11

C

G11C 8/00 (2006.01) G11C 8/12 (2006.01)

Patent

CA 2127947

A memory is partitioned into rows and columns of memory blocks comprised of latches, sense amplifiers, and logic circuitry that form independent pipelines through which flow a) input addresses for memory access requests and b) data to be written into a specific memory cell within a memory block. The memoryallows multiple data access requests in consecutive clock cycles to be pipelined in the rows and columns of memory blocks such that the memory clock speed is equal to the clock speed of a single memory block, independently of the memory size.

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