Gallium arsenide logic design system

Details Gallium arsenide logic design system Gallium arsenide logic design system

H - Electricity

03

K

328/127

H03K 19/08 (2006.01) H01L 27/06 (2006.01) H03K 19/0185 (2006.01) H03K 19/0956 (2006.01)

Patent

CA 1292784

A GALLIUM ARSENIDE LOGIC DESIGN SYSTEM ABSTRACT OF THE DISCLOSURE A gallium arsenide logic design system is described for designing custom or semi-custom LSI integrated circuits using standard cells from a cell library. D-MESFET transistors and Schottky diodes are used for implementing the cell types in gallium arsenide to produce performance levels of less than 150 pico- seconds per gate propagation delay. Each integrated circuit die is built from a cell library containing three standard cells. The limitation on the number of standard cells used for logic design allows for fast and efficient turnaround time between logic design and fabrication. A minimum number of masks are required for implementing the custom integrated circuit due to the efficient design of the cell types. The placement and interconnect of the cells on the die are also performed in an efficient manner due to the predefined allowable locations for cell placement and the predefined allowable route channels for the interconnect. A clock amplifier cell is also described for the cell library which differentially phase corrects a two-phase clock signal to ensure that the two clock lines are perfectly out of phase at all times. The com- bination of this strictly controlled two-phase clock with the gallium arsenide cell designs allows digital logic implementations at an LSI level to operate at 1-GHz clock frequencies.

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