Gate biasing arrangement

Details Gate biasing arrangement Gate biasing arrangement

H - Electricity

03

F

H03F 1/30 (2006.01)

Patent

CA 2359679

To eliminate the temperature dependency of the quiescent current of a power transistor (1), the gate bias voltage of the power transistor (1) is controlled by means of the output voltage of a biasing transistor (3) residing on the same silicon chip as the power transistor (1), and by interconnecting the gate (G3) and drain (D3) of the biasing transistor (3) and feeding it with a constant current (IB) from external circuitry.

Afin d'éliminer la sensibilité à la température du courant de repos d'un transistor de puissance (1), on régule la tension de polarisation de la grille de ce transistor de puissance (1) à l'aide de la tension de sortie d'un transistor de polarisation (3), placé sur la même puce de silicium que ledit transistor de puissance (1), et on interconnecte la grille (G3) et le drain (D3) dudit transistor de polarisation (3) tout en fournissant à ce dernier un courant constant (IB) depuis des circuits extérieurs.

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