Gated parallel decoder

Details Gated parallel decoder Gated parallel decoder

H - Electricity

03

K

328/139

H03K 19/08 (2006.01) H03K 19/017 (2006.01) H03K 19/0948 (2006.01) H03K 19/096 (2006.01)

Patent

CA 1170319

RCA 75,990 GATED PARALLEL DECODER Abstract of the Disclosure The decoder includes a plurality of input signal responsive transistors having their conduction paths connected in parallel between a node and a point of reference potential. These transistors, when turned-on, tend to clamp the node to the reference potential. A controllable load is connected between a second voltage and the node for providing when,enabled by an external control signal and in the absence of an internally generated inhibit signal, a conduction path to charge the node towards the second voltage. The inhibit signal, generated by an inhibit network responsive to the node voltage, inhibits conduction via the charging conduction path of the controllable load when the node voltage is at, or close to, the second voltage.

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