Gating circuit

Details Gating circuit Gating circuit

H - Electricity

03

K

328/132

H03K 19/00 (2006.01)

Patent

CA 1171472

ABSTRACT A gating circuit for gating a minimum duration input signal on one of a plurality of input lines (10) to a respective output line (16). The input lines (10) are coupled to a latch (15) comprising flip-flops and the latch is enabled when a signal is applied to a clock input (18). The input lines (10) are coupled to a verifier circuit (25) which includes a verifier gate (27) receiving direct and delayed signals from a NAND gate (32) connected to the input lines (10). The verifier gate (27) applies a signal to the clock input (18) when both inputs (28,29) are simultaneously receiving a signal so that signals less than the minimum duration do not result in a signal at clock input (18). The NAND gate (41) applies a signal to locking gate (44) when any one output (16) of latch (15) is energised, and the output (47) of locking gate (44) holds a disabling signal on clock input (18) so that only the first input signal on a line (10) will be latched. A reset means (50) including reset gate (51) and switch (53) enables resetting of the latch (15).

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