Glitch lockout circuit for memory array

Details Glitch lockout circuit for memory array Glitch lockout circuit for memory array

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G11C 7/00 (2006.01) G11C 7/12 (2006.01) G11C 7/14 (2006.01) G11C 7/24 (2006.01) G11C 11/40 (2006.01) G11C 11/4094 (2006.01) G11C 11/419 (2006.01)

Patent

CA 1229917

-11- GLITCH LOCKOUT CIRCUIT FOR MEMORY ARRAY Abstract The present invention relates to a glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase. The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

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