G - Physics – 01 – R
Patent
G - Physics
01
R
324/58.1
G01R 31/28 (2006.01)
Patent
CA 1198774
GO/NO GO MARGIN TEST CIRCUIT FOR SEMICONDUCTOR MEMORY ABSTRACT A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each connected to one input of a sense amplifier (146, 148). The sense amplifiers (146, 148) operate to pull one of the half digit lines connected thereto to ground while a pull up circuit (220) operates to elevate the other half digit line to the supply voltage. A margin test circuit receives through a control pin (236) an externally supplied test command which generates a test signal (318) to generate marginal low and marginal high voltage states to be written into the memory cells. The marginal low voltage state is generated by a voltage divider (288). The marginal high voltage state is generated by disabling the pull up circuit (220). To prevent loss of the marginal low state the sense amplifiers (146, 148 and 248) are disabled by the internally generated test signal. While the externally supplied test command is applied to the semiconductor memory circuit (140) marginal voltage states are applied to memory cells in accordance with externally supplied address and operational commands. The marginal voltage states are utilized to simplify testing of the circuit.
385263
Mostek Corporation
Smart & Biggar
LandOfFree
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