Graphic processor having multiple geometric operation units...

G - Physics – 06 – F

Patent

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G06F 13/12 (2006.01) G06F 19/00 (2006.01) G06T 15/00 (2006.01) G09G 5/36 (2006.01)

Patent

CA 2323116

A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include an arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.

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