Graphics processing unit with shared arithmetic logic unit

G - Physics – 06 – T

Patent

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G06T 1/20 (2006.01)

Patent

CA 2666064

This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

La présente invention concerne un pipeline d'unité de traitement graphique (GPU) utilisant une ou plusieurs unités arithmétiques logiques (ALU) partagées. Afin de faciliter ce partage des ALU, les phases du pipeline GPU décrit peuvent être réordonnées par rapport aux pipelines GPU conventionnels. De plus, en réordonnant les phases du pipeline GPU, on optimise les rendements dans le traitement d'images. À la différence des pipelines GPU conventionnels, par exemple, une phase de spécification des gradients d'attributs peut être placée beaucoup plus tard dans le pipeline, et la phase d'interpolation d'attributs peut suivre immédiatement la phase de spécification des gradients d'attributs. Ceci permet le partage d'une ALU par les phases de spécification des gradients d'attributs et d'interpolation d'attributs. L'invention concerne également plusieurs autres techniques et caractéristiques pour le pipeline GPU, susceptibles d'améliorer les performances et éventuellement de réaliser des gains de rendement du traitement.

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