Grid array masking tape process

Details Grid array masking tape process Grid array masking tape process

H - Electricity

01

L

H01L 21/78 (2006.01) H01L 21/302 (2006.01) H01L 21/304 (2006.01) H01L 21/68 (2006.01)

Patent

CA 2119505

GRID ARRAY MASKING TAPE PROCESS ABSTRACT OF THE DISCLOSURE Active sites (18) on a semiconductor wafer (14) are protected from particulate and fluid contaminants (40,42) while the wafer (14) is sawed into chips (16) by a tape (62) carrying a pattern of adhesive (64) which is congruent and registerable with saw paths (15) between the active sites (18). Adhering the tape (62) to the wafer (14) encapsulates each active site (18) in a non-adherent protective envelope which includes adhesive-free portions (68) of the tape (62) as sawing occurs along the saw paths (15) and the adhesive (64). After sawing, the adhesive (64) is treated, as by directing UV through the tape (62), to release the tape (62) from the chips (16). -38-

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