Hardware arrangement for enciphering bit blocks while...

Details Hardware arrangement for enciphering bit blocks while... Hardware arrangement for enciphering bit blocks while...

G - Physics

09

C

G09C 1/00 (2006.01) H04L 9/06 (2006.01)

Patent

CA 2118826

A plaintext is enciphered using a plurality of stages in tandem via a plurality of iterations. Each of the stages is arranged to perform a complex key-dependent computation. The stage includes a memory for storing a key. A cipher function circuit transposes, using the key, one block applied to the stage from a preceding stage. An exclusive-or circuit implements an exclusive- or operation of the output of the cipher function and the other block applied to the stage from the preceding stage. A unique arrangement is provided for transposing the output of the cipher function circuit and then applying the output thereof to the memory. Therefore, the key is replaced with the output of the unique arrangement.

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