Hardware demand fetch cycle system interface

Details Hardware demand fetch cycle system interface Hardware demand fetch cycle system interface

G - Physics

06

F

354/231, 354/239

G06F 9/00 (2006.01) G06F 9/22 (2006.01) G06F 9/30 (2006.01)

Patent

CA 1284387

ABSTRACT OF THE DISCLOSURE A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

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