Hermetic protection of integrated circuits

Details Hermetic protection of integrated circuits Hermetic protection of integrated circuits

H - Electricity

01

L

H01L 23/29 (2006.01) H01L 23/28 (2006.01) H01L 23/31 (2006.01)

Patent

CA 2106694

HERMETIC PROTECTION FOR INTEGRATED CIRCUITS ABSTRACT The present invention relates to hermetically sealed integrated circuits. These circuits comprise a circuit subassembly having a primary passivation and one or more bond pads opened in the passivation. To the primary passivation is applied a silicon containing ceramic layer by a physical vapor deposition (PVD) or CVD process. In addition, the ceramic layer also covers a portion of the bond pads such that the opening is smaller than that present in the primary passivation and the bond pads, are thereby, more effectively sealed.

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