Heterostructure bipolar transistor

Details Heterostructure bipolar transistor Heterostructure bipolar transistor

H - Electricity

01

L

H01L 29/737 (2006.01) H01L 21/285 (2006.01) H01L 51/30 (2006.01) H01L 51/40 (2006.01)

Patent

CA 2529595

An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47)As contact layer 9 heavily doped with Si are stacked on a substrate 1.

L'invention porte sur un procédé consistant à superposer sur le substrat (1) une couche sous-collectrice (2) de InP dopée avec une concentration élevée de silicium (Si) pour conversion en type n, une couche collectrice (3) de InP, une couche de base (4) de GaAs<sub

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