Hierarchical integrated circuit cache memory

Details Hierarchical integrated circuit cache memory Hierarchical integrated circuit cache memory

G - Physics

11

C

G11C 7/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2043493

A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits, each of which includes a portion of the primary cache memory, a portion of the secondary cache memory, and data path circuits interconnecting the portions of the primary and secondary memories to portions of a data processor port and a main memory port. The primary cache memory, for example, includes ECL memory elements, and the secondary cache memory includes CMOS memory elements. In a preferred construction, the primary cache memory has address input lines wired in parallel to address input lines of the secondary cache memory, and data input lines wired in parallel to data input lines of the secondary cache memory. The data input lines of the cache memories are connected to data output lines of a parallel/serial shift register having a parallel input connected to data output lines of the secondary cache memory, and a serial data input connected to the main memory port. For write-back of data, the serial/parallel shift register includes an additional parallel input connected to data output lines of the primary cache memory, and an additional parallel input connected to the data processor port.

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