Hierarchical memory controller

Details Hierarchical memory controller Hierarchical memory controller

G - Physics

06

F

G06F 12/08 (2006.01) G06T 15/00 (2006.01)

Patent

CA 2055784

A memory apparatus including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to at least one other serially stored instruction, accessing at least one remaining buffer.

Dispositif à mémoire comprenant un circuit de réception et de stockage en série d'une pluralité d'instructions et plusieurs mémoires tampon comprenant chacune un contrôleur de tampons pour réguler l'accès à ces mémoires. Le dispositif comprend également un circuit relié à chaque contrôleur de tampons et au circuit de réception, afin de permettre un accès à une ou plusieurs mémoires tampon en réponse à au moins une autre instruction stockée en série, et pour accéder à au moins une mémoire tampon restante.

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