G - Physics – 06 – F
Patent
G - Physics
06
F
356/134
G06F 17/50 (2006.01)
Patent
CA 1275508
A B S T R A C T HIERARCHICAL TOP-DOWN METHOD FOR PHYSICAL VLSI-CHIP DESIGN For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip needs no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.
554556
Klein Klaus
Pollmann Kurt
Schettler Helmut
Schulz Uwe
Wagner Otto M.
International Business Machines Corporation
Na
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