High accuracy mos comparator

Details High accuracy mos comparator High accuracy mos comparator

H - Electricity

03

K

328/169

H03K 5/22 (2006.01) H03F 3/16 (2006.01) H03K 3/353 (2006.01) H03K 3/356 (2006.01) H03K 5/24 (2006.01)

Patent

CA 1072644

HIGH ACCURACY MOS COMPARATOR Abstract of the Disclosure The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to an FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

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