High availability cache memory

Details High availability cache memory High availability cache memory

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G06F 12/08 (2006.01) G06F 12/12 (2006.01) G06F 13/20 (2006.01) G06F 11/00 (2006.01) G06F 11/10 (2006.01) G06F 11/20 (2006.01)

Patent

CA 1320285

Abstract of the Disclosure HIGH AVAILABILITY CACHE MEMORY A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.

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