High density josephson junction memory circuit

Details High density josephson junction memory circuit High density josephson junction memory circuit

G - Physics

11

C

352/49, 352/82

G11C 11/44 (2006.01) H01L 39/22 (2006.01)

Patent

CA 1214270

ABSTRACT OF THE DISCLOSURE A superconductive Josephson junction high density memory array is provided. Each memory cell in the array comprises a two branch superconducting interferometer storage loop which has only a single Josephson junction device in one of the branches. The Josephson junction devices are mounted on a substrate having a patterned ground plane. The ground plane pattern is provided with holes or apertures which surround the Josephson junction devices so that the control current of the control lines couple with the tunnel junctions of the Josephson junction devices but not with the ground plane. This structural arrangement provides a threshold characteristic for the single Josephson junction device which is symmetrical to the gate current, thus, may be easily switched to two current states indicative of two logic states.

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