High density multi-layer circuit arrangement

H - Electricity – 05 – K

Patent

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H05K 1/14 (2006.01) H05K 1/00 (2006.01) H05K 1/11 (2006.01) H05K 3/40 (2006.01) H05K 3/42 (2006.01) H05K 3/46 (2006.01)

Patent

CA 1228933

A HIGH DENSITY MULTI-LAYER CIRCUIT ARRANGEMENT ABSTRACT An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors divided into at least two conductor groups by a transversely oriented break across each conductor. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface and is also divided into at least two conductor groups by a transversly oriented break across each conductor. A plurality of holes extend through the first layer with, each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated-through holes has conductor pennants extending from selected holes in a first direction on the top sur- face and a second opposite direction on the bottom surface. A plurality of first and second layers are sandwiched together, with each hole of each layer in registration with the other and each conductor pennant contacting a respective first layer conductor. Conductor segments printed on the second layer top and bottom surfaces inter- connect selected conductors between respective conductor groups. Additionally, two or more second layers are interconnected by via pins extending through the arrange- ment.

479496

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