G - Physics – 11 – C
Patent
G - Physics
11
C
352/82
G11C 17/00 (2006.01) G11C 17/12 (2006.01)
Patent
CA 1265868
Abstract of the Disclosure An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select ore of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder means, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder means, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.
526168
Glasser Lance A.
Mazin Moshe
Sano Jun-Ichi
Glasser Lance A.
Mazin Moshe
Raytheon Company
Sano Jun-Ichi
Smart & Biggar
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