High density rom in a cmos gate array

Details High density rom in a cmos gate array High density rom in a cmos gate array

G - Physics

11

C

352/82.24

G11C 17/00 (2006.01) G11C 17/12 (2006.01) H01L 27/112 (2006.01) H01L 27/118 (2006.01)

Patent

CA 1307049

ABSTRACT OF THE DISCLOSURE A memory circuit implemented in a CMOS gate array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETS that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.

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