High density semiconductor chip organization

Details High density semiconductor chip organization High density semiconductor chip organization

H - Electricity

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H01L 27/10 (2006.01) H01L 23/48 (2006.01) H01L 27/118 (2006.01) H01L 29/06 (2006.01) H03K 19/173 (2006.01)

Patent

CA 1061009

HIGH DENSITY ARCHITECTURE FOR A SEMICONDUCTOR CHIP Abstract A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magni- tudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensi- tive logic systems which utilize both combinatorial as well as sequen- tial networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.

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