High density semiconductor circuit layout

Details High density semiconductor circuit layout High density semiconductor circuit layout

H - Electricity

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H01L 23/48 (2006.01) H01L 23/528 (2006.01) H01L 27/118 (2006.01) H03K 19/084 (2006.01) H03K 19/088 (2006.01) H03K 19/091 (2006.01)

Patent

CA 1064624

HIGH DENSITY SEMICONDUCTOR CIRCUIT LAYOUT Abstract An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in con- tiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direc- tion and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially iden- tical identical geometric form and arranged in columnar arrays. - 1 -

268098

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