High frequency, low power, cmos circuit

Details High frequency, low power, cmos circuit High frequency, low power, cmos circuit

H - Electricity

03

K

H03K 19/00 (2006.01) G06F 1/08 (2006.01) G06F 1/32 (2006.01)

Patent

CA 2110048

2110048 9320618 PCTABS00027 Power dissipation of a CMOS circuit such as a microprocessor is reduced by dynamically slowing down the microprocessor clock (CLKOUT) during selected system operations such as hold, wait or ATperipheral bus access cycles. The microprocessor clock (CLKOUT) is slowed to its minimum allowable frequency with precise synchronous control to maintain the accuracy of high frequency clock edges and to prevent glitches or substandard pulse widths.

Affiliated with

Also associated with

Rating

High frequency, low power, cmos circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High frequency, low power, cmos circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High frequency, low power, cmos circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1566392