High performance bubble chip architecture

Details High performance bubble chip architecture High performance bubble chip architecture

G - Physics

11

C

352/37.2

G11C 19/08 (2006.01)

Patent

CA 1178370

SA9 30 043 HIGH PERFORMANCE BUBBLE CHIP ARCHITECTURE Abstract of the Disclosure A major/minor loop bubble memory system architecture includes a passive replicator in the major loop read chan- nel which is connected by a first path to a mode switch- annihilator and a merge point in the major loop write channel and by a second path to an off-chip decision-making means and the merge point in the write channel. The decision-making means is positioned the same or fewer propa- gation steps than the mode switch-annihilator is from the replicator. The decision making means is activated to cause either the replicated data to pass through the mode switch- annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.

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