G - Physics – 06 – F
Patent
G - Physics
06
F
354/111
G06F 11/10 (2006.01) G11C 8/10 (2006.01)
Patent
CA 1271559
YO987-018 HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORIES ABSTRACT OF THE INVENTION A high performance decoder/driver circuit for a semiconductor memory having Al to AN (true) and ?? to ?? (complement) address lines for receiving Al to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to Al to AN-1 or ?? to Image of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and ?? lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.
582215
Chappell Barbara A.
Chappell Terry I.
Schuster Stanley E.
International Business Machines Corporation
Rosen Arnold
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