High-performance, high-density cmos decoder/driver circuit

Details High-performance, high-density cmos decoder/driver circuit High-performance, high-density cmos decoder/driver circuit

G - Physics

06

F

352/81

G06F 12/02 (2006.01) G11C 7/00 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1223352

HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT ABSTRACT A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and ?? to ?? (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 of ?? to ???? of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.

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