High performance latch circuit

Details High performance latch circuit High performance latch circuit

H - Electricity

03

K

328/138

H03K 3/286 (2006.01) H03K 3/287 (2006.01) H03K 3/288 (2006.01) H03K 19/08 (2006.01)

Patent

CA 1076218

HIGH PERFORMANCE LATCH CIRCUIT Abstract of the Disclosure Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The out- put node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advan- tageously implemented in semiconductor integrated circuit technology. .. . . . _ ..... .. . ...... .. . ~ . . . . . . . . . . . . .... ....... .... . . . . . .. . .

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