High performance low pin count bus interface

Details High performance low pin count bus interface High performance low pin count bus interface

G - Physics

06

F

354/231

G06F 13/40 (2006.01)

Patent

CA 1297991

HIGH PERFORMANCE LOW PIN COUNT BUS INTERFACE ABSTRACT An interface system between a high speed user bus and a system bus is provided to present to the user bus a picture of the data transferred on the system bus every clock cycle of that system bus. The interface system also allows the user bus to transfer data back to the system bus during selected bus cycles. By using a single pin connection to the system bus, the user bus can send communications back to itself by way of the system bus.

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