High performance memory imaging network for a real time...

H - Electricity – 04 – L

Patent

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Details

CPC

340/84

IPC codes

H04L 12/28 (2006.01) G06F 13/36 (2006.01) G06F 13/37 (2006.01) H04L 12/66 (2006.01)

Type

Patent

Patent number

CA 1331791

Description

32 ABSTRACT OF THE DISCLOSURE A data communications arrangement for a distrib- uted processor control system having a number of stations which can send and receive control data, includes a commu- nications processor at each station effective for control- ling the flow of control data over a serial communications bus. The communications processor is coupled to a dual ported memory device along with a functional processor which is effective for carrying out the actual operations of the process. The communications control processor is further effective for assembling frames of control data according to a predetermined arrangement which gives a timing preference to a first category of data over a second category of data. The assembled frame of control data will then include all of the first category of data and, with time remaining from a timing goal, will include a portion of the second category of data.

Application Number

601254

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