High performance, small area thin film transistor

Details High performance, small area thin film transistor High performance, small area thin film transistor

H - Electricity

01

L

356/149

H01L 29/78 (2006.01)

Patent

CA 1234227

ABSTRACT OF THE DISCLOSURE A high performance, small area thin film transistor has a drain region, an insulating layer, and a source region at least portions of the edge of which form a non-coplanar surface with respect to a substrate. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel be- tween the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The length of the current conduction channel is deter- mined by the thickness of the insulative layer and therefore can be made short without precision pho- tolithography. The non-coplanar surface can be formed by utilizing a dry process to simultaneous- ly etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source re- gion by creating two capacitances in series, thereby limiting further the capacitance between the gate electrode and the source region. -1-

498522

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