High performance speculative misaligned load operations

Details High performance speculative misaligned load operations High performance speculative misaligned load operations

G - Physics

06

F

G06F 9/30 (2006.01) G06F 9/312 (2006.01) G06F 13/20 (2006.01)

Patent

CA 2260308

One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.

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