High speed binary and decimal adder

Details High speed binary and decimal adder High speed binary and decimal adder

G - Physics

06

F

354/198

G06F 7/50 (2006.01)

Patent

CA 1101124

Abstract of the Disclosure A high speed binary and decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.

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