High speed buffer memory system with word prefetch

Details High speed buffer memory system with word prefetch High speed buffer memory system with word prefetch

G - Physics

06

F

354/246

G06F 9/22 (2006.01) G06F 12/08 (2006.01) G06F 12/12 (2006.01) F02B 75/02 (2006.01)

Patent

CA 1123521

ABSTRACT A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.

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