G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/16 (2006.01) G06F 15/167 (2006.01) G06F 15/173 (2006.01)
Patent
CA 2042711
HIGH SPEED BUS SYSTEM Abstract A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.
Derosa John
Keller James B.
Ramanujan Raj
Samaras William A.
Stewart Robert E.
Derosa John
Digital Equipment Corporation
Keller James B.
Ramanujan Raj
Samaras William A.
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